The present invention relates to a method of manufacturing a semiconductor device such as a MOS (Metal Oxide Semiconductor).
In a manufacturing method of a semiconductor device such as a MOS, photolithographic technology has been widely employed. In the photolithographic technology, an insulating film 1 is first formed on a surface of the silicon wafer W, as shown in FIG. 1A. A photoresist film 2 is then formed on the insulating film 1 as shown in FIG. 1B. The photoresist film 2 is exposed to light and developed to form a pattern on the resist film 2, as shown in FIG. 1C. Using the patterned resist film 2 as a mask, the insulation film 1 is selectively etched as shown in FIG. 1D, followed by removal of the photoresist film 2 as shown in FIG. 1E. Then, as shown in FIG. 1F, the pattern formation surface of the wafer W is covered with a wiring layer 3. Subsequently, an unnecessary portion of the wiring layer 3 is removed from the surface by chemical mechanical polishing. In this manner, a predetermined circuit pattern is formed.
To etch the insulating film 1 accurately and faithfully to a predetermined pattern in the step of FIG. 1D, it is important for the photoresist film 2 left on the wafer W to have a sufficient thickness to serve as a masking material. If the photoresist film 2 is not sufficiently thick, the resist film 2 is partially etched away together with the insulating film during etching. As a result, the contrast of the resist pattern decreases and the masking function thereof degrades. Therefore, the photoresist film 2 is formed on the insulating film 1 in a thickness of at least 100 to 150 nm (1.0 to 1.5 .mu.m) in the step shown in FIG. 1B of a conventional method.
On the other hand, according to a circuit design standard for a semiconductor device in recent years, a wiring width required for 16M-DRAM falls 50 to 60 nm (0.5 to 0.6 .mu.m) and the wiring width required for 64M-DRAM is 35 nm (0.35 .mu.m). To attain such an ultra-fine micro patterning, an even higher resolution level is required during light-exposure, with the result that the focus margin of a light exposure device has become very narrow. Under this circumstance, it has been difficult to bring the photoresist film 2 of 100 to 150 nm thick into focus of a light exposure device. Accordingly, a highly accurate ultra-fine micro pattern formation is not attained. It is therefore useful to reduce the thickness of the photoresist film 2 as much as possible to form such an ultra-fine micro pattern. However, if the photoresist film 2 is formed excessively thin, not only the insulating film 1 but also the photoresist film 2 is etched away during etching. The resultant resist pattern decreases in contrast, failing in masking function.
Recently, a chemically amplified resist has been widely used since it can compensate shortage in brightness. However, the chemically amplified resist has a disadvantage in that light permeability is slightly lower than a novolac series resin generally used. Therefore, if the chemically amplified resist film is formed thick, it takes a long time to complete the light-exposure process. The light exposure process must be carried out in a short time to increase the throughput. In consideration of throughput, it is desired that the chemically amplified resist film be formed as thin as possible.
In addition, in the conventionally employed process, a photoresist film 2 must be removed in the step of FIG. 1E before the step shown in FIG. 1F. This is because when the contact hole 3 is formed through the insulating film 1 with the photoresist film 2 left thereon, the depth of the contact hole 3 is deeper than required, with the result that the wiring layer 4 may not smoothly reach a bare silicon surface of the wafer W. For this reason, it has been desired that the resist film be formed even thinner.
On the other hand, the photoresist film 2 forming the side wall of the contact hole 3 shown in FIG. 1D is influenced by a polymer attached thereon and sometimes behaves like a hard material on appearance. As a result, after the photoresist film 2 is removed, a side wall portion 2a remains in the form of a fence as shown in FIG. 1E. Therefore, a step of removing the fence-form side wall portion 2a must be added after the step shown in FIG. 1E. Since a process step is added, the throughput decreases. In addition, care must be taken to dispose of an organic solvent used in removing the fence-form side wall portion so as not to have adverse effects on other agents and the wafer.